(1) Field of the Invention
The present invention relates to methods used to fabricate semiconductor devices, and more specifically to a process used to control the doping profile of the channel region, in a lateral direction, formed via ion implantation procedures, in the channel region of a metal oxide semiconductor field effect transistor, (MOSFET), device.
(2) Description of Prior Art
The continuing objective of increasing device density, and increasing device performance, via micro-miniaturization, or via the use of sub-micron features for MOSFET devices, has led the semiconductor devices has directed the semiconductor industry to the fabrication of MOSFET device with channel lengths as narrow as 0.18 um, Although the use of MOSFET devices, featuring narrow channel lengths, have satisfied the density and performance objectives of the semiconductor industry, formation of specific regions of the sub-micron MOSFET devices, such lightly doped source/drain, (LDD), regions, as well as an anti-punchthrough region, located in the channel region of the MOSFET device, have become more difficult to achieve and control For example the ion implantation, used to form the LDD, or source/drain extensions, can result in encroaching, sphere-like profiles, sometimes decreasing the designed channel length, or effective channel length, (Leff), to an undesirable length of less than 0.18 um. In addition, subsequent high temperature processing steps, can result in lateral diffusion of the LDD regions, again resulting in an undesirable shortening of the channel length. For these reasons a lateral delta doping region, or an anti-punchthrough region, is placed in the channel region, between LDD regions to insure the integrity of the dimension of the channel length, as well as to minimize jointing, or touching of the depletion regions created at the junction of the LDD regions, and the semiconductor substrate.
This invention will describe a process for forming a lateral delta doping region, which has the added advantage of serving as an anti-punchthrough region, between LDD regions. However this invention will feature an anti-punchthrough region that will consume less lateral space in the channel region, than counterpart anti-punchthrough regions, fabricating without the use of this invention, thus still reducing the LDD jointing phenomena, however also reducing the capacitance generated with larger area, anti-punchthrough regions. The smaller area, or truncated, anti-punchthrough region, is formed via a novel process sequence, featuring the formation of spacers, on the sides of a trench shape, which will subsequently be used to accommodate a polysilicon gate structure, followed by the anti-punchthrough ion implantation procedure, placing the lateral delta doping region in an area of the subsequent channel region, reduced in lateral dimension by the presence of the spacers. Prior art, such as Lee et al, in U.S. Pat. No. 5,856,225, shows a anti-punchthrough region formed in a trench, with the trench next filled with a polysilicon gate structure. In that prior art however the critical gate insulator layer, as well as the critical sidewall spacers, are subjected to the removal of the dummy gate structure, and thus used as part of the final gate structure. In contrast this invention does not feature the use of a dummy gate structure, and therefore the gate insulator layer, and sidewall spacers, are not formed prior to the anti-punchthrough region, and therefore are not subjected to the processes used to form and to remove, the insulator shape, which in turn is used to provide the trench needed for definition of the MOSFET polysilicon gate structure.